 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| sames FEATURES n SA2030 SA2030 PCM FRAME ALIGNER Frame Alignment Recovery and loss in accordance with CCITT recommendations G.732 and G.737 Jitter and phase-wander immunity exceed the requirements of CCITT recommendation G.823. Internal 11/2 frame elastic buffer. Detection of incoming AlarmIndication-Signal (AIS), and Distant Alarm n Indication of Slip, loss of frame synchronisation, and loss of route clock conditions. ISO-CMOS Compatible. technology, TTL n n n n Pin-for-Pin replacement for Siemens PEB 2030 and SM 300 Microprocessor Interface n n APPLICATIONS n Delay compensation and clock alignment between 2,048MHz PCM30 transmission lines, and terminating equipment. Control of Jitter and Wander within Digital Networks. n Delay compensation between switching stages. Interfacing of PCM systems operating with different clocks. PCM concentrators and subscriber multiplexers. n n n GENERAL DESCRIPTION The SA2030 is designed to interface PCM-30 routes with switching systems. The device synchronises with the frame-format of the incoming data, and outputs this data in accordance with the bit and frame timing of the terminating equipment. The circuit is designed to tolerate delay, drift, wander and jitter of the incoming data and clock, and thus simplifies the design of data- and clock-recovery hardware. The internal 11/2 frames elastic buffer provides for delay compensation and wander immunity. If the bounds of the buffer are exceeded, the SA2030 will either repeat or drop a frame. The circuit will accurately detect incoming Alarm-Indication-Signal (AIS) conditions, in accordance with CCITT recommendation G.737. Loss of frame alignment is indicated on both dedicated outputs and by outputting of AIS. The circuit includes a bidirectional alarm port for interrogation of alarm conditions. M74-1885 sames 1/12 20.01.93 SA2030 PIN CONFIGURATION BLOCK DIAGRAM 2/12 sames SA2030 FUNCTIONAL DESCRIPTION PCM INPUT AND FRAME-ALIGNMENT The SA2030 accepts route data on the IN input pin, on rising edges of the route clock RCL. The circuit synchronises with the frame format of the incoming data by identification of the Frame Alignment Signal (FAS) and the Service Word (SW) in time slot zero of the PCM frame. The algorithm used for recovery and loss of frame synchronisation is in accordance with CCITT recommendation G.737. After the circuit has gained synchronisation with the incoming PCM-30 data stream, it outputs a synchronisation pulse SP on alternate frames, during the bit interval prior to time-slot-zero of frames containing the FAS word. The circuit will output a fault pulse on the FP output every time errors are detected in the incoming FAS word. When the circuit is unable to synchronise with the incoming data format, the SA2030 will generate a fault pulse every alternate frame, and outgoing synchronisation pulses will be suppressed. PCM OUTPUT Data is clocked out on falling edges of the System Clock (SCL). PCM output is clocked out serially on the SO output, and is made available in parallel on a tristate bus with parity (B1-B8, P). The tristate outputs are enabled by asserting CE. The SA2030 must be provided with a System Clock Trigger (SCT) pulse to define the required output frame timing. The SCT pulse defines the bit interval immediately prior to the start of time-slotzero, on every alternate frame. Acceptance of SCT pulses is only enabled when CE is asserted. The tristate parallel bus, with CE control, simplifies the use of the circuit in multiplex and switching applications. ELASTIC BUFFER Incoming PCM data is saved in dual-ported RAM. The RAM has capacity for 11/2 frames of data. The SA2030 can thus accommodate any required frame delay between the incoming data timing, and the required output frame timing. When the bounds of the buffer are exceeded, whole frames are either dropped or repeated. The action of dropping or repeating a received frame is called slip. Depending on the frame-delay, the SA2030 can tolerate between 1/2 and 11/2 frame of wander without requiring to alternately repeat and drop frames. The design of the elastic buffer controller provides for correct performance under severe clock-and-data-jitter conditions. The SA2030 exceeds the requirements of CCITT recommendation G.823, and can be used to control jitter and wander within digital networks. The 11/2 frame buffer is enabled by setting BI = 0. If BI = 1, the buffer length is limited to only one frame. The frame delay through the framealigner is then constrained to be less than one frame. The buffer inhibit mode is useful for delay compensation within a switching system, where drift and wander do not occur. sames 3/12 SA2030 ALARM SUBSYSTEM The alarm system may be used by the host equipment to determine the operation status of the SA2030. The SA2030 provides a bidirectional alarm-port interface DB1 and DB2. The direction of the interface is controlled by the R/W line. Transfers to or from the interface are enabled by strobing the port-enable (PE) input. The circuit includes two 2bit alarm registers. The four flags in these registers are set when: * Incoming Alarm-Indication-Signal is received (AIS) Loss of frame synchronisation occurs (SYLOSS) A distant alarm is received (DISAL) A frame slip occurs (SLIP) The algorithm used for detection of incoming AIS is in accordance with CCITT recommendation G.737. That is, AIS will be correctly detected, even in the presence of random errors, at a rate of 1 in 103. The loss of frame synchronisation flag is set if loss of frame-alignment occurs, if the route clock is missing or too slow, or if a system-clock-trigger (SCT) pulse is not applied to the circuit once every alternate frame. The distant alarm flag is set if bit 3 of time-slot-zero of frames not containing FAS is true. The frame-slip is set if the frame aligner either drops or repeats a frame. * * * Selection of which of the two alarm registers is to be read, is carried out by first writing a command to the comand register via DB1 and DB2. Four commands are supported: Enable Read of Alarm Group 1 Enable Read of Alarm Group 2 Clear all alarm flags Simulate Alarms Alarm Group 1 includes the AIS and frame synchronisation flags. Alarm Group 2 includes the Slip and distant alarm flags. Once an alarm flag is set, it can only be cleared by writing the "clear-all-alarms" command to the alarm command register. That is, these flags remain set until explicitly cleared. The simulate-alarm command provides an alarm system self-test capability. This command simulates all alarm conditions at their sources. If the circuit is operating correctly, all alarm flags should be set after issuing this command. Alarm simulation tests the loss of synchronisation function of the frame alignment state-machine, and the AIS detection logic, and thus may require up to four-frames to complete. After all of the alarm flags are set, alarm simulation is disabled, and the circuit reverts to normal operation. 4/12 sames SA2030 LOSS AND RECOVERY OF FRAME ALIGNMENT CONDITIONS R Good FAS Received R One or more errors in FAS M Bit 2 of service word = 1 (Good SW) M Bit 2 of service word = 0 (Bad SW) UXS Unsynchronised stated U0S, U1S or U2S M2S Two service word errors received state STATES U0S U1S U2S S0S S1S S2S M0S M1S M2S - Unsynchronised, zero frames OK state Unsynchronised, one frame OK state Unsynchronised, two frame OK state Synchronised, zero FAS errors state Synchronised, one FAS error state Synchronised, two FAS errors state Zero service word errors state One service word error state Two service word errors state 5/12 sames SA2030 Command Mnemonic RAG1 RAG2 CLR SIM Write DB2 0 0 1 1 DB1 0 1 0 1 Alarms Read DB2 AIS SLIP DB1 SYLOSS DISAL - Description Read Alarm Group 1 Read Alarm Group 2 Alarm Register Clear Simulate Alarms Notes: 1. After the CLR or SIM commands, neither RAG1 or RAG2 are selected for reading. Thus subsequent reading will return undefined data. 2. Allow 4 frames for the SIM command to execute before issuing a RAG1 or RAG2 command. 6/12 sames SA2030 PIN DESCRIPTION Pin No. Name Function 1 2 3 DB1 DB2 SP Bidirectional Alarm Port Bidirectional Alarm Port Synchronisation Pulse output. Asserted during the bit interval immediately prior to time-slot-zero of frames that contain FAS. Suppressed in the event of frame-alignment loss. Input for controlling direction of Alarm port data bus DB1 and DB2. Internally pulled up to VDD. Alarm port enable. Asserting this pin enables data transfers to or from DB1 and DB2. Internally pulled up to VDD. Route Clock Input. 2.048 MHz clock that defines PCM input data timing. The route clock is usually extracted from the route data. System Clock Input. 2.048 MHz clock that defines the timing of the terminating equipment. Buffer Inhibit Input. When true, the 11/2 frame buffer is inhibited, and the output frame timing is constrained to be within one-frame of the input frame timing. When false, the full 11/2 frame buffer is enabled, and immunity to wander is maximised. Buffer Inhibit Mode of operation is intended for delay compensation between switching stages in one exhange system. Internally pulled up to VDD. Station Clock Trigger input. Low going pulse used by the host system to define the required output frame timing. SCT should be asserted on alternate frames, during the data-bit interval immediately prior to timeslot-zero. SCT input is enabled by asserting CE. Chip Enable input. When asserted the parallel outputs, B1 to B8 and P are enabled. When CE = 1, parallel outputs are high impedance. CE must also be asserted to enable the SCT input. Internally pulled-up to VDD. Serial PCM Data Output. PCM-30 format output of aligned and retimed data. Data clocked out under control of the System Clock SCL. Ground (0V) supply. Parity Bit 3-state Ouput. Parity check for internal RAM. RAM data is saved with Parity bit. Even Parity is used. 3-State PCM Parallel Output (PCM sign bit). 3-State PCM Parallel Output 3-State PCM Parallel Output 3-State PCM Parallel Output 3-State PCM Parallel Output 3-State PCM Parallel Output 3-State PCM Parallel Output 3-State PCM Parallel Output (LSB) PCM data input. Data is derived from route data and is clocked into the circuit on rising edges of RCL. Fault Pulse Output. Fault pulses of 4 Route Clock cycles duration are delivered whenever errors are detected in FAS, or on alternate frames in the event of Frame Alignment loss. Supply Voltage (+5V Nominal) 4 5 6 7 8 R/W PE RCL SCL BI 9 SCT 10 CE 11 12 13 14 15 16 17 18 19 20 21 22 23 SO VSS P B1 B2 B3 B4 B5 B6 B7 B8 IN FP 24 VDD sames 7/12 SA2030 Absolute Maximum Ratings Characteristics Supply Voltage Voltage on any pin Storage Temperature Total power dissipation Operating ambient temperature range Sym VDD VPIN TSTG PTOT T OP Min -0,3 VSS -0,3 -55 0 Max 7,0 VDD +0,3 125 100 70 Unit V V C mW C Conditions 25C - Stresses beyond these limits may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Recommended Operating Conditions Characteristics Supply voltage Voltage on any pin Operating temperature Sym VDD VPIN TOP Min 4,75 VSS 0 Typ 5,00 25 Max 5,25 VDD 70 Unit V V C Conditions - Electrical Characteristics TAMB = 25C, over recommended operating supply voltage range. Characteristics Standby Power Consumption Power Consumption Sym PSTBY P OPER Min - Typ 25,0 Max 1,0 - Unit mW mW Test Conditions Outputs, Unloaded, VDD = 5V Outputs Unloaded, at 2,048MHz, VDD = 5V Input High Voltage Input Low Voltage Input Pull-up Current Output High Voltage Output Low Voltage High Impedance Leakage Current VIH VIL IPU VOH VOL IOZ 2,4 -150 2,7 - 50 0,8 -5 0,4 - V V A V V nA VIN = 0V IOH = -1,0mA IOL = 1,0mA 8/12 sames SA2030 Route Subsystem Timing (At VDD = 5V, TAMB = 25C) Characteristics Route Clock Period Route Clock Duty Cycle Input Data Setup time Input Data Hold time Synch Pulse Width Synch Pulse Delay Fault Pulse Width Fault Pulse Delay Synch Pulse Repeat Period Fault Pulse Repeat Period Sym TRCL DRCL tS tH tSPW tDOSP tFPW t DOFP TSP TFP Min 400 25 150 40 - Typ 488 50 488 1952 250 250 Max 600 75 200 200 - Unit ns % ns ns ns ns ns ns s s Test Conditions Note 1, 2, 3 at 2,048MHz In Frame Synch In Frame Synch After Bad FAS After Bad FAS In Frame Synch Out of Frame Synch Note: 1. The CCITT recommends clock frequency of 2,048MHz 50ppm. 2. Incorrect Slip operation may occur if the Route clock and System clock differ by more than 1% (10000ppm). 3. A Synch Alarm will be issued if the Route Clock frequency is less than 75% of the Station Clock frequency. Route Subsystem Timing Diagram sames 9/12 SA2030 Alarm Port Read / Write Timing (At VDD = 5V, TAMB = 25C) Characteristics Data Setup Time Write Enable Setup Time Port Enable Write Setup Time Data Hold Time Write Enable Hold Time Port Enable Hold Time Write Duration Read Enable Setup Time Port Enable Read Setup Time Read Access Time High Impedance Delay Sym tDE tWE tWPE tED tEW tWEP tN tRE tRPE tRA tEDZ Min 100 150 150 100 100 100 444 150 150 Typ 896 Max 350 160 Unit ns ns ns ns ns ns ns ns ns ns ns Test Conditions at 2,048MHz CL=50pF, RL=5K Note: 1. R/W and PE are read on rising edges of SCL. 2. Data is latched on failing edges of SCL subject to R/W = 0, and PE = 0 on previous SCL rising edge. 3. Data is output after rising edge of SCL subject to R/W = 1 and PE = 0. Alarm Port Write Timing Diagram 10/12 sames SA2030 Alarm Port Read Timing Diagram Data Output Timing (at VDD = 5V, TAMB = 25C) Characteristics System Clock Period System Clock Duty Cycle Clock Trigger Setup Time Clock Trigger Hold Time SO Output Delay BI.. B8, P Output Delay Note: 1. Sym tSCL DSCL tST tHT tDOSO tDOB Min 400 25 150 100 Typ 488 50 Max 600 75 200 200 Unit ns % ns ns ns ns Conditions Note 1 CL=15pF, RL=10K CL=15pF, RL=10K The CCITT recommends a data rate of 2,048MHz + 50ppm. sames 11/12 SA2030 JITTER IMMUNITY FRAME DELAY 12/12 sames |
Price & Availability of SA2030
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |